Modern semiconductor devices including integrated circuit devices have electrically conductive leads and output drivers which are switched ON and OFF. The switching operations between no current and peak current is very rapid and may cause rapid changes in the power supply voltage and spikes within the lead circuits and die circuits. Such induced voltage and current variations cause malfunctions of the integrated circuit and may severely limit the clock speed at which the device can be satisfactorily operated. The problem is particularly relevant in devices having a large number of leads, where many leads may be simultaneously switched ON to cause a large, sudden current drain.
The goal of decoupling capacitors is to provide a condition whereby the actual ranges of voltage and current in each part of the circuit in the ON and OFF stages are relatively narrow. The de-coupling capacitor provides necessary current demands of the chip during operation. If the de-coupling capacitance is not enough, the inductance of the power delivery line might cause voltage dipping which could result in the malfunction of the chip. Currently, most of the VLSI chips rely on parasitic capacitance (i.e. N-well junction capacitance) to provide the major part of the necessary on chip de-coupling capacitance. In some highly integrated VLSI circuits where the instantaneous current demand is high, additional de-coupling capacitors are added in the surrounding area of peripheral circuitry to stable the power supply in case of heaving switching activities occurring on chip. With the increasing usage of SOI (Silicon-on-Insulator) technology, the problem of voltage dipping is particular acute, because SOI technology inherently has less parasitic capacitance.
Decoupling capacitors are frequently used in the supply rail of the on-chip cache memory blocks inside the processor chip due to high current demand during cache access from the CPU.
FIG. 1 illustrates a floor-plan view of a conventional microprocessor 10. The microprocessor 10 has logic 16 and cache circuitry 14. The logic circuitry 16 is the plurality of boxes located in the center of the figure (D MMU, LSU, IFV, FXU, DU, BP, IFV, FPU, PLL and MMU). The logic circuitry 16 includes the processor and other features involved in carrying-out processing functions of the microprocessor 10. The cache circuitry 14 is the plurality of boxes labeled “cache”. The cache circuitry 14 is a well known in the art memory device. Decoupling capacitors 12 surround the logic 16 and cache 14 circuitry so as to provide load energy/storage so that the sudden current demand required by the circuitry does not result in a draining of a distant power supply (not shown). The use of decoupling capacitors 12 are well known in the art and will be discussed with greater detail with regards to FIGS. 2–4.
The coupling of the logic circuitry 16 and cache circuitry 14 in the conventional microprocessor 10 allows recently used data or instructions in the cache to be readily available to the processor, instead of requiring the processor to search for the data or instructions as in the case where distant, slow Dynamic Random Access Memory (DRAM) is used. Typically, the decoupling capacitors 12 are located along side or placed in various locations among the logic and cache circuitry, as shown in the figure. The area above the logic and cache circuitry contains metal inter-connection and inter-layer dielectric material.
In today's VLSI processor class, such as the Pentium 4 or PowerPC, the on-chip cache often occupies a large amount of chip area. In some cases, the total cache size takes more than two thirds of the chip area. Also, the processors tend to run at high frequencies, typically in the GHz range. Integrated circuits operating at such high frequencies are frequently susceptible to various forms of interference, such as, signal coupling and radio frequency interference. Typically, to avoid such interference in the memory block, a substantial amount of space above the circuit structure is left unused for signal routing, This space can be a useful location for de-coupling capacitor construction.
The prior art is replete with methods to counter this problem. Most of the prior art attempts to overcome the above stated problems by increasing the chip area to accommodate a larger de-coupling capacitance. One of the advantages of SOI technology is the small parasitic capacitance which results in small de-coupling capacitances. However, the solutions put forth by the prior art tend to be costly.
A cost effective solution has been sought for providing on chip de-coupling capacitors circuits in integrated circuits and solve the power supply and interference problems in the chip.